Machine Learning Engineer - Chip Design Automation

What You'll Do

Build predictive models for PPA & Timing

Develop ML models to predict Power, Performance, Area, and timing violations critical paths, setup/hold slack at early RTL and synthesis stages to reduce costly signoff iterations.

Automate Physical Design

Apply Reinforcement Learning RL and Graph Neural Networks GNNs to automate and optimize placement, routing, and floorplanning.

Process Chip Data at Scale

Work directly with circuit netlist formats Verilog gate-level, LEF/DEF, SPEF, SDC, Liberty to build graph-based representations for ML consumption.

Deploy Closed-Loop ML

Integrate trained ML models as closed-loop plugins within industry EDA tool scripts e.g., Tcl plugins so your predictions actively drive and influence real-time design decisions.

Predict Manufacturability

Build DRC hotspot prediction models to catch lithography and design rule violations pre-tapeout.

Build Data Pipelines

Architect pipelines to extract, label, and learn from massive simulation outputs generated by standard VLSI synthesis and physical design tools.

Collaborate Cross-Functionally

Partner with RTL, physical design, and mixed-signal verification teams to identify bottlenecks and deploy your AI-assisted tooling into production flows.

What We're Looking For

Required

• 3-6 years of ML/AI engineering experience or exceptional academic background/Masters/PhD focused on ML for EDA .
• Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field with a GPA of 9+ from IITs, NITs, BITS, or IISc.
• Deep ML/AI Expertise: Strong proficiency in Python and deep learning frameworks PyTorch or TensorFlow , specifically with experience in graph-based ML GNNs, graph transformers on structured relational data.
• Domain Knowledge STA & Physical Design : Solid understanding of Static Timing Analysis STA concepts-timing paths, slack margins, clock trees, and signoff criteria-as well as the broader ASIC/SoC RTL-to-GDSII flow.
• EDA Data Fluency: Proven ability to parse and manipulate chip design data formats LEF/DEF, SPEF, SDC, Liberty, gate-level Verilog .
• Automation & Scripting: Advanced proficiency in scripting languages heavily used in EDA Tcl, Python, Perl, Bash .
• End-to-End Ownership: Proven ability to take ML systems from data collection and training to inference and deployment.

Preferred

• Prior experience applying ML to EDA algorithms using data from commercial tools Synopsys, Cadence, or Siemens EDA .
• Understanding of mixed-signal circuits, wireless communication blocks, or low-power DSP design.
• Published research at top AI/ML or EDA venues DAC, ICCAD, NeurIPS, ICML, ISPD, etc. .

Compensation & Benefits

• Base salary: Competitive and based on experience
• Cash bonus + meaningful early‑stage equity
• Relocation bonus, partner job‑search help
• Health insurance, paid leave, performance incentives, and employee rewards

Why Join Us

• Work on deep tech that matters
• Collaborate with world-class experts and industry leaders
• Own your work end-to-end and see real impact
• Enjoy a culture of speed, rigor, and respect
• Competitive salary, equity, and global exposure

Keywords

Machine Learning, Graph Neural Networks, Reinforcement Learning, Static Timing Analysis, Physical Design, RTL to GDSII, PPA Optimization, Verilog, Tcl Scripting, EDA Tools