96106-1- ASIC Frontend

q ID 10790936

Job Title: Engineer

Work Location: ~~HYDERABAD~

Skills Required: EIS : ASIC Frontend - Modeling, RTL design and Implementation

Experience: 4-6

Role Descriptions: FPGA RTL Designer Strong experience in RTL design using Verilog/SystemVerilog.Solid understanding of digital design fundamentals and computer architecture.Experience with FPGA development flows from RTL to bitstream generation.

Essential Skills: FPGA RTL Designer Strong experience in RTL design using Verilog/SystemVerilog.Solid understanding of digital design fundamentals and computer architecture.Experience with FPGA development flows from RTL to bitstream generation.

Desirable Skills

Keyword

Skills: EIS : ASIC Frontend - Modeling RTL design and Implementation

Experience Required: 4-6