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Senior E/E & Semiconductor Engineer - Senior Physical Design Engineer|Texas|5+Yrs

  • Capgemini
  • United S...
  • 5 - 10 Yrs

Job Closed

Job Description

  • Job Role: Senior Engineer – Physical Verification
  • Master Degree in Electrical or Electronics Design Engineering
  • Minimum 5 years of experience in running physical verification tools and resolving any issues with CAD Vendor and/or Foundary.
  • Experience in using Synopsys advanced physical Verification tools.
  • Experience in running physical verification tools for lower nodes like 5nm or below.
  • UPF based low power implementation.
  • Experience in Place and route, STA preferrable
  • Scripting experience with Python, Tcl or Perl
  • Mandatory skills and skill proficiencies:
  • ICV Validator or Caliber (siemens) or Virtuoso (Cadence) - Any one proficiency
  • Optional skills:
  • ICC/ICC2, Primetime, STAR-RC, Python, TCL or Perl
  • Synopsys Physical Design tools – ICC/ICC-2, Primetime, STAR-RC, Python, TCL or Perl
  • Have 5 years of experience with Synopsys Physical Design tools – ICC/ICC-2, Primetime, STAR-RC
  • Have years of experience with Physical Design related to ASIC/SOC

Job Responsibilities

  • You will be responsible for running DRC tools like IC-Validator on subsystem physical Design database for TSMC 5nm, 3nm and 2nm nodes.
  • You will directly work with CAD vendor and Foundry to resolve any issues related to DRC errors.
  • You will run Physical verification tool like Synopsys IC Validator to compare Layout vs Schematics (LVS)
  • You will be responsible to fix PDV/EMIR/Noise/SigEM violations and errors.
  • DRC/LVS/ERV/ANTENNA analysis and clean up.
  • Floorplan analysis and congestion solution
  • Power IR/EM analysis and fix
  • Physical Verification signoff


Location

Texas, United States