Physical Design Engineer – Full Chip Floorplanning (FCFP)

Job Title: Physical Design Engineer – Full Chip Floorplanning (FCFP)

Location: Bangalore

Experience: 8–15 Years

Job Description

We are looking for an experienced Physical Design Engineer – Full Chip Floorplanning (FCFP) to join our VLSI team. The ideal candidate should have strong expertise in full-chip floorplanning, physical implementation, timing closure, and advanced technology nodes.

Key Responsibilities

• Perform full-chip floorplanning and chip integration.
• Handle macro placement, IO planning, and power planning.
• Drive placement, CTS, routing, and timing closure.
• Analyze and resolve congestion, DRC, IR drop, and EM issues.
• Collaborate with design, STA, and verification teams to achieve successful tape-out.

Required Skills

• Full Chip Floorplanning
• Macro Placement
• Power Planning
• IO Planning
• Placement, CTS & Routing
• Timing Closure
• Congestion Analysis
• IR/EM Analysis
• ICC2 or Cadence Innovus
• Tcl Scripting
• Experience with advanced technology nodes (5nm/7nm/12nm/16nm) is preferred.

Preferred Qualifications

• Bachelor's or Master's degree in Electronics, VLSI, or a related field.
• Experience in multiple SoC/ASIC tape-outs is an added advantage.

If you have hands-on experience in Full Chip Physical Design and are looking for an exciting opportunity, we'd love to hear from you.

Apply Now!

Pay: From ₹1,500,000.00 per year

Benefits

• Flexible schedule
• Leave encashment
• Life insurance
• Provident Fund

Work Location: In person