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DFT Engineer - Design for Testability|Multiple|4+Yrs

  • Overture Rede
  • Multiple
  • 4 - 6 Yrs

Job Closed

Job Description

  • Minimum of 4+ years of experience in Design for Testability (DFT) for integrated circuits.
  • Strong understanding of DFT concepts and methodologies, including scan insertion, BIST, ATPG, and memory test.
  • Proficiency in using Electronic Design Automation (EDA) tools for DFT implementation and verification.
  • Experience with scripting languages (Perl, TCL) for automation purposes (a plus).
  • Excellent analytical and problem-solving skills.
  • Strong communication and collaboration skills to work effectively with cross-functional teams.

Job Responsibilities

  • Scan Design & Verification :
  • Implement scan insertion techniques to improve test coverage and controllability of internal logic within the IC design.
  • Perform thorough scan chain verification to ensure proper functionality and identify potential scan path defects.
  • Built-In Self-Test (BIST) & Memory BIST :
  • Design and integrate BIST structures into the IC for autonomous testing of internal components.
  • Implement and validate Memory BIST solutions for efficient and comprehensive memory testing.
  • Automatic Test Pattern Generation (ATPG) :
  • Utilize ATPG tools to generate test patterns that target potential faults and achieve high test coverage.
  • Analyze and optimize test patterns for efficiency and effectiveness.
  • IP & Pattern Validation :
  • Collaborate with IP vendors to ensure proper DFT implementation within the integrated IP blocks.
  • Validate test patterns for both functional and timing correctness, with and without timing constraints.


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