Job Description & Responsibilities

Understanding of DFT architectures like Boundary scan (JTAG), Scan Compression Techniques (XOR, Adaptive, OP-MISR etc. ), scan chain insertion and verification.
Must have experience generating scan patterns and coverage statistics for various fault models like stuck at (Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, and pattern generation for Memories (E-fuse etc. ).
Experience in Coverage Analysis.
Synopsys tools: DFT MAX, TetraMAX, VCS Cadence tools: Genus, Modus, Xcelium. Mentor Graphics tools: Tessent toolchain, TestKompress.
Should be responsible for the cross-functional issues and dependencies across RTL integration, synthesis, constraints, timing analysis and related analysis and debugs.
Familiar with Verilog and RTL simulation.
Good Knowledge of Spyglass.
Experience with gate-level pattern simulations and debugging.
Exposure to post-silicon debugging is a plus.
Scripting skills: Perl, TCL.

DFT Engineer (ATEM)|Bangalore|1+Years

Job Description & Responsibilities